Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to a semiconductor device having a barrier metal between a metal layer and an interlayer insulating film and its fabrication method.
Description of the Related Art
The multilayer wiring technologies have been used in various semiconductor devices. The recent demands for miniaturization of semiconductor devices have resulted in various multilayer wiring technologies. An example of the wirings is a damascene technology disclosed in Carter W. Kaanta et al., DUAL DAMASCENE: A ULSI WIRING TECHNOLOGY, VMIC Conference, IEEE, pp. 144-pp. 152. This technology uses copper as a plug metal in a contact hole formed in an interconnection metal and an interlayer insulating film. A barrier metal is employed between the plug metal and the interlayer insulating film in order to prevent the plug metal from being diffused into the interlayer insulating film.
A conventional multilayer wiring process with copper will now be described with reference to FIGS. 1(a) through 1(d) and FIGS. 2(a) through 2(c), which are cross-sectional views showing the process. Referring to FIG. 1(a), a lower interconnection layer 16 is formed above a semiconductor substrate (not shown). The lower interconnection layer 16 extends laterally in FIG. 1(a), and has a major component of copper. An interlayer insulating film (not shown) that underlies the lower interconnection layer 16 appears in regions between the lower interconnection layers 16. A silicon nitride layer 20 is formed on the lower interconnection layer 16 and the underlying interlayer insulating film, and a silicon oxide film 22 serving as the interlayer insulating film is formed on the silicon nitride layer 20.
Referring to FIG. 1(b), contact holes are formed in the interlayer insulating film 22. Referring to FIG. 1(c), a barrier layer 24 is formed in the contact holes and the interlayer insulating film 22. Copper is deposited to form a seed layer (not shown) on the barrier layer 24 by sputtering. Copper is grown on the seed layer by plating. Referring to FIG. 1(d), the wafer is polished up to the interlayer insulating layer 22 by CMP so that the wafer surface is flattened. This results in plug metals 26 in the contact holes.
Referring to FIG. 2(a), a silicon nitride film 30 serving as an etching stopper is formed on the interlayer insulating film 22. Referring to FIG. 2(b), a silicon oxide film serving as an interlayer insulating film 32 is formed on the silicon nitride film 30. Referring to FIG. 2(c), openings are formed in the interlayer insulating film 32, and seed layers (not shown) and interconnection layers 34 having a major component of copper. Then, the wafer is polished up to the interlayer insulating film 32 by CMP. By the above process, one interconnection layer is completed. The process may be repeatedly carried out for multilayer wiring.
However, the above conventional art has the following problems. The same barrier layer as the barrier layer 24 between the plug metals 26 and the interlayer insulating film 22 is formed between the plug metals 26 and the interlayer insulating layer 16. This results in a large contact resistance between the plug metals 26 and the interlayer insulating film 16. Further, the barrier layer 34 exists between the interconnection layer 36 and the plug metals 26, and increases the contact resistance therebetween.